module counter(
	// common
	m_rst_n_i,
	m_clk,

	// count
	m_cnt,

	// system
	cnt_log
	);

// common signals
input 			  m_rst_n_i;
input 			  m_clk;
// count
output	  [7:0]   m_cnt;
// system
input 	  [31:0]  cnt_log;

reg 	  [7:0]   m_cnt;
always@(posedge m_clk or negedge m_rst_n_i)
begin
  if(!m_rst_n_i)
  begin
	m_cnt <= 0;
	$fdisplay(cnt_log, "%t : counter reset, m_cnt = 0", $time);
  end
  else
  begin
	m_cnt <= m_cnt + 1;
	$fdisplay(cnt_log, "%t : m_cnt = %d", $time, m_cnt);	
//	$fdisplay(cnt_log, "%t : m_cnt = %d", $time, m_cnt+1);
  end
end

endmodule


module test();

reg 			  rst;
reg 			  clk;
wire	  [7:0]   cnt;

integer 		  log_file_desc, output_file_desc;

counter cnt1 (
	// common
	.m_rst_n_i				(!rst),
	.m_clk					(clk),
	
	// count
	.m_cnt					(cnt),

	// system
	.cnt_log				(output_file_desc)
	);

initial
begin
  //open log files
  log_file_desc = $fopen("counter.log");				// multichannel descriptor, the first call will return ...10
  if(log_file_desc < 2)
  begin
	$display("*E Could not open/create testbench log file in ./ directory!");
	$finish;
  end

  output_file_desc = log_file_desc | 1;	//also print to standout output
  
  // reset pulse  
  rst = 1'b1;
  #20 rst = 1'b0;
end

// clock
initial begin
  clk = 0;
  forever #5 clk = ~clk;
end

initial begin
  #300
	$display("\n\n END of Simulation !");
  	$display("\n ########## the detailed info printed to counter.log ########## \n");
	$fclose(log_file_desc);						//close multi channels : $fclose(tb_log_file | mem_log_file | xxx_log_file); 
	$stop;
end


endmodule